1. Field of the Invention
The present invention relates to the fabrication methods used for semiconductor devices, and more specifically to the process used to, achieve narrow polycide gate dimensions.
2. Description of Prior Art
The semiconductor chip industry is continually striving to reduce costs, while still increasing circuit performance. These objectives have been met by the ability of the industry to reduce critical chip images to sub-micron dimensions resulting in more chips per silicon wafer, thus reducing cost. In addition the reduction of critical chip dimensions has also resulted in improved device performance. For example the performance of conventional metal oxide semiconductor, field effect transistors, (MOSFET), devices is strongly dependent on the critical dimension of the gate image. The device performance increases as the channel length decreases. The requirement to produce narrow gate features, with close spacing between adjacent features, is strongly dependent on the photolithographic processes used in the chip fabrication process. Advances in the photolithography technology have been achieved via more sophisticated cameras, allowing for greater resolution, in photoresist materials, to be achieved. In addition the development of more high contrast photoresist materials has also contributed to the trend to smaller images. However a problem caused by the reflectivity of materials, underlying the photoresist, have caused degradation to occur in the photoresist images through reflective light scattering.
The light scattering phenomena, resulting in the degradation of the desired photoresist image, is not only a function of the underlying material causing the undesirable reflections, but is also influenced by the topography of the structure the photoresist image is to be generated on. For example thick field oxides, used for device isolation purposes, result in topographies that adversely effect subsequent photoresist imaging. Specifically the critical dimension of the MOSFET gate, in turn influencing the critical channel length dimension, can be difficult to achieve due to light scattering during photoresist exposures. The reflectivity of specific materials, overlying the severe topography created by the thick field oxide, is increased due to this topography. The solution to the topography problem is to either use chemical-mechanical polishing to reduce the topography, or to use a shallow trench oxide isolation process. Both of the above solutions result in increased process complexity and cost.
Another solution to the scattered light phenomena is the use of an anti-reflective coating, (ARC), layer, which reduces or minimizes the magnitude off reflective light and thus allows critical dimensions in photoresist to be achieved. There are several options for the use of ARC layers. For example the use of a TiN layer, inserted between the photoresist and the underlying gate material, has found much use in the fabrication of MOSFET chips. However this option adds considerable cost to the product since the TiN used is disposable. That is after the resist image has been used as a mask to define the underlying gate structure the TiN has to be removed. It should also be noted that device performance can also be degraded due to the presence of metallic ions sometimes found in TiN layers. In addition the adhesion between the photoresist and the TiN ARC layer has to be considered. Another version of an ARC layer described by Chen, etal, in U.S. Pat. No. 4,933,304 uses a "roughened" surface of a metal layer, between the photoresist and the underlying gate material. Sandhu, etal, in U.S. Pat. No. 5,139,974 also describe a process for decreasing the optical reflectivity of a metal layer by "roughening" the metal surface. The roughened surface reduces reflections from the underlying gate material that would otherwise result in light scattering and undesirable exposure of the critical photoresist dimension. The step of toughening the surface includes deposition of an additional metal film and a plasma step to form the uneven surface. Again these steps add complexity and cost to the product, and can sometimes result in device performance degradation.
The invention now to be described uses ASPARC, (an Amorphous Silicon film on Polycide gates as an Anti-Reflective Coating). This invention will show two iterations, one in which the ASPARC layer is removed after use, and the other in which the ASPARC film remains as a part of the final gate structure. This process and structure described in this invention are easy to implement and are compatible with the polycide gate process being used.